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FAQ
Short answers to the questions that come up most often.
Short answers. Each one links to the page with the full story.
About the product
Which languages can it write?
Verilog and SystemVerilog everywhere, and VHDL in Plan mode from a scratch workspace. See Language and target device.
Is the output synthesisable?
That is the target, and every run with Auto-Verify on is pushed through synthesis to check. Treat the result as a reviewed draft rather than as signed-off IP; you are still the engineer of record.
Can it work on code I already have?
Yes, through project mode: upload a zip and it edits your files in place and returns a diff. See Upload a project.
Do I get a testbench?
With Auto-Verify on, yes, and it is self-checking; it reports pass or fail rather than leaving you to read waveforms. See Auto-Verify.
Do I need a simulator installed?
No. Compilation, simulation and synthesis all run on our side; you get the logs and the files.
Billing
What does the free tier actually include?
Every feature, limited only by the $1.00 of credit you start with, which is roughly three real runs. No card is required. See Plans and packages.
Am I charged for a run that failed?
A run that did real work settles at what it cost, whether or not it produced a module you liked. A run that never started is released rather than charged. Your ledger shows which happened.
Do tools cost extra?
They do not add runs. A generation with every tool on is one run; it takes longer, and on the free tier it costs a little more because free-tier runs settle at measured cost.
What happens when my allowance runs out?
Runs continue at $0.85 each from credit. With no credit either, new runs are refused up front rather than started and abandoned.
Working with it
Agent or Plan?
Agent when the next step depends on the last one, and for anything involving an existing project. Plan when you want to be asked about the ambiguities first, or when you need VHDL. See Agent mode and Plan mode.
Can one chat build a whole design?
One module per chat works best from scratch, because verification is built around a single design under test. For a multi-module design, use project mode; that is what it is for.
Can I attach a datasheet?
Not yet from the composer; the paperclip says so. Quote the part you need in the spec, or include the document in a project upload. See Knowledge base.
Can I share a result?
Yes, as a read-only link that needs no account. See Sharing a chat.
Is there an editor integration?
A VS Code extension is in progress. The pages for it in this guide are placeholders until it ships.
Data
Is my work private?
Chats are private to your account; the only way to expose one is to create a share link. See Privacy and analytics.
How long are my files kept?
Generated files stay with their chat until you delete it. Uploaded project workspaces are cleaned up on a schedule; see Limits and retention.