Getting started
Introduction
What RTLBridge does, who it is for, and how to find your way around these docs.
RTLBridge turns a plain-language description of a hardware block into RTL you can actually use. You write a sentence or a paragraph about what the module should do; RTLBridge writes the Verilog or VHDL, builds a self-checking testbench, runs the simulation, checks that the design synthesises, and hands you every file it produced.
What you get from a run
A finished run is not a code snippet in a chat window. It is a small set of files that belong together, and you can download all of them at once:
- The module. Synthesisable Verilog, SystemVerilog or VHDL, written against the interface you described.
- A testbench. Self-checking, so it reports pass or fail rather than leaving you to read waveforms.
- A simulation log. The raw output of the simulator, so you can see exactly what was exercised.
- A synthesis report. A rough resource estimate against the device family you picked.
Everything lives in a chat, so you can keep asking for changes; each follow-up starts from what the previous one produced.
Who this is for
RTLBridge is built for people who already know hardware. It assumes you can read RTL, spot a bad reset, and tell whether a testbench covered the case you cared about. What it removes is the typing: the boilerplate module header, the third FIFO this month, the testbench you keep meaning to write.
If you are new to RTL, the output is still useful as a starting point, but treat every module as a draft to review rather than as a verified deliverable.
The screen you will spend time in
Almost all of the product is one screen with three columns. The sidebar on the left holds your chats and the links to settings, billing and these docs. The middle is the conversation. The panel on the right holds the files a run produced.
Conversation
Your request, the run's progress, and the summary of what it built. The composer sits at the bottom.
Files
Module, testbench, simulation log, synthesis report.
A run, at a glance
Every generation walks the same seven steps. You can watch them tick across as the run progresses, and a failed run stops on the step that broke:
| Step | What happens |
|---|---|
| SPEC | Your request is read and turned into a concrete interface and behaviour. |
| RTL | The module is written. |
| REVIEW | The model re-reads its own output and fixes what it finds; only when Reflection is on. |
| TESTS | A test plan and a self-checking testbench are produced. |
| SIM | The design and testbench are compiled and simulated. |
| SYNTH | The design is pushed through synthesis for a resource estimate. |
| FILES | Everything is written out and attached to the chat. |
How to read these docs
If you have five minutes, read the Quickstart and generate something. If you want to understand why a run behaves the way it does, How RTLBridge works is the page that explains the machinery. Everything else is reference material you can come back to.