Configuring a run
Run setup
The panel that holds every per-run choice, and how it relates to your saved defaults.
Run setup is the panel that holds every choice a run makes: mode, tools, models, output language and target device. It slides in from the right and applies to the run you are about to start.
Opening it
Three ways in, all the same panel:
- The small line above the composer that reads something like Verilog · AMD / Xilinx.
- Run setup at the bottom of the Tools menu.
- The keyboard-free route: anywhere the current configuration is shown as a summary.
Run setup
Configure this generation.
Mode
Context & retrieval
Verification
Generation
Output language
Target device
What is in it
| Section | What it controls |
|---|---|
| Mode | Agent or Plan; see Agent mode and Plan mode. |
| Context & retrieval | The four switches that decide what the run may read; see Tools overview. |
| Verification | Auto-Verify and Reflection. |
| Generation | The three model roles; see Choosing models. |
| Output language | Verilog or VHDL; see Language and target device. |
| Target device | The vendor family the synthesis estimate is measured against. |
The quick controls on the composer
The three things people change most often are also on the composer itself, so you rarely need the panel: the Agent / Plan toggle, the model picker, and Tools. The tools menu is the same set of switches in a shorter form.
Context & retrieval
Web Search
✓Exa Search
IP Core Library
Knowledge Base (RAG)
Verification
✓Auto-Verify
Reflection
Per-run choices and saved defaults
Run setup changes the run in front of you. To change what every new chat starts with, open Settings and use the Setup section; it holds the same controls and writes them to your saved defaults.
Tip
If you always want Auto-Verify on, set it in Settings rather than switching it on every time. Run setup then only exists for the exceptions.
When a control is locked
Some combinations are not valid, and the interface removes the choice instead of letting you make it and then rejecting the run:
| Situation | What changes |
|---|---|
| Project mode | The mode toggle becomes a fixed Agent label, and the language is Verilog. |
| Agent mode | VHDL is unavailable; the agent loop is Verilog only. |
| VHDL selected | IP Core Library and Knowledge Base are unavailable for that run. |