Existing projects
Upload a project
Package your RTL, drop it in, and check what RTLBridge actually took from the archive.
Project mode drops RTLBridge into your own code. You upload a zip, describe the change you want, and it explores the files, edits them in place, runs what it can, and hands you a diff. Nothing is rewritten from scratch and nothing outside the archive is touched.
Packaging your project
Zip the folder that contains your RTL. A zip exported from a Git host works as-is; the single wrapper directory those produce is unwrapped for you.
fifo_project.zip
├── rtl/
│ ├── fifo.sv
│ ├── fifo_pkg.sv
│ └── sync_fifo_ctrl.sv
├── tb/
│ └── fifo_tb.sv
├── docs/
│ └── interface.md
└── README.md- Include the testbenches. A run that can execute your tests is far more useful than one that cannot.
- Include the short design notes. Anything explaining intent is read the same way a new colleague would read it.
- Leave out build output and dependency folders. They are filtered anyway, and they slow the upload down.
Uploading
- 1
Switch the workspace to Existing project
The toggle sits above the composer on a new chat. A dropzone appears under it.
- 2
Drop the zip, or press to pick one
The upload starts as soon as the file is chosen, before you write anything. That is on purpose: you see exactly what was accepted before spending a run.
- 3
Check the resolved tree
You get the file count, the total size, whether a wrapper directory was unwrapped, and the full list of files that were taken.
fifo_project.zip
9 files · 42.6 KB · unwrapped fifo_project-main/
- rtl/fifo.sv
- rtl/fifo_pkg.sv
- rtl/sync_fifo_ctrl.sv
- tb/fifo_tb.sv
- README.md
show 4 more
2 skipped
- 4
Read the skipped list
Anything rejected is listed under N skipped. If a file you need is in there, fix the archive and upload again rather than running and wondering.
- 5
Describe the change and press Generate
Project mode always uses the agent loop, so there are no clarifying questions; it answers those from your files.
What to ask for
Requests read differently here than in a scratch chat. You are describing a change to something that exists, so naming the file or the module is usually enough context:
- Add an enable input to the counter in rtl/counter.sv and thread it through the top level.
- The FIFO reports full one entry early. Find out why and fix it.
- Write a self-checking testbench for sync_fifo_ctrl and run it.
- Which module drives axi_awready, and under what conditions?
Tip
A question is a perfectly good request. Asking what a signal does costs a cheap conversational call rather than a full run, and it does not change any files.
The workspace persists across turns
This is the main difference from a scratch chat. Edits accumulate: the second turn starts from the files the first one left behind, the third from the second, and so on. You are working in one directory over the whole conversation, not re-deriving it each time.
You do not need to re-upload anything for a follow-up, and you should not; the chat already knows which workspace it belongs to.
Restrictions
| Restriction | Why |
|---|---|
| Agent mode only | The staged pipeline is built around a single generated module. |
| Verilog and SystemVerilog only | The agent loop does not target VHDL. |
| One project per chat | A chat is bound to its workspace; start a new chat for a different project. |
Asking for Plan mode or VHDL alongside a project is refused rather than silently downgraded, so a run never quietly does something other than what you selected.